1. Field of the Invention
This invention generally relates to frequency synthesis and, more particularly, to a system and method for generating an N.5 divider, where N is an integer.
2. Description of the Related Art
Phase-Locked-Loop (PLL)—A circuit using a reference frequency and feedback to control a high frequency output signal.
Fractional-N—A circuit that varies the divide ratio of a divider between two or more integer values, allowing the overall average division ratio to be a fraction between the integer divide ratios.
Modulus Counter—A counter that can change its divide ratio on-the-fly. Normally, the counter is limited to a few values such as divide by (2 or 3) or divide by (4 or 5), etc.
Phase Frequency Detector—A circuit that outputs an analog voltage set by the phase and frequency of the two inputs, the reference clock and the PLL divider block. If the reference clock is faster in frequency or sooner in phase, the circuit outputs a positive voltage to speed up a voltage controlled oscillator (VCO). Should the PLL divider signal be faster in frequency or sooner in phase, then it output a negative signal slowing down the VCO.
Voltage Controlled Oscillator (VCO)—An oscillator with an output frequency that is controllable by an analog voltage input supplied by a phase frequency detector.
Delta Sigma—A circuit that provides dithering or a pseudo random variation in divide ratios to reduce spurs.
Spurs (spurious frequencies)—Undesired frequency components in the VCO's output signal due to the interaction of the reference frequency signal mixing with the counter output frequency.
FIG. 1 is a schematic diagram of a phase-locked loop (prior art). A modulus counter 100 divides the VCO 102 signal by N. Even if N is an integer, the delta sigma circuit 104 may cause the modulus counter to dither, creating an average divisor N. For example, the modulus counter may divide by (N+1) 50% of the time and (N—1) 50% of the time. In this example, counter 106 divides by integer M.
FIG. 2 is a schematic diagram of a simplified modulus counter, which divides by N in FIG. 1 (prior art). An input signal is applied to the logic block 200, which then monitors the clock out signal and inputs the proper signal to the first flip-flop 202. This circuit is a very simple example. Modulus dividers can consist of several flip-flops and can exist in chains of several individual modulus divider blocks. Existing modulus dividers are limited to divide by N ratios, hence are coarse in the divide ratios they can provide, resulting in high spurs and large voltage swings at the output of the phase detector.
It would be advantageous if a modulus counter had the added the ability to divide by N.5, as well as N, adding the flexibility of a greater number divide ratios for use in a fractional-N PLL.
It would be advantageous if a divide by N.5 ratio could be added to a modulus counter, to reduce the amplitude of generated spurs by as much as 6 dB.